During the formation of a semiconductor device, various types of contacts, for example to a wafer substrate or word line, are commonly formed. FIGS. 1-3 depict a wafer at various stages during a conventional method for simultaneously forming a portion of a transistor and contacts to a word line and to a wafer substrate.
FIG. 1 shows a wafer assembly formed using conventional processing steps comprising the following layers: a wafer substrate 10, a gate oxide layer 12 formed over substrate 10, a polycrystalline silicon (poly) layer 14 formed over gate oxide 12, a tungsten silicide layer 16 overlying poly 14, an oxide separation layer 18 formed between silicide 16 and a nitride layer having a first portion 20A formed over the front of the wafer substrate 10 and a second portion 20B formed over the back of the wafer substrate 10, and a layer of spacer material having a first portion 24A formed over the front of the wafer substrate 10 and a second portion 24B formed over the back of the wafer substrate.
A spacer etch can be performed on the FIG. 1 structure to form spacers 30 as shown in FIG. 2, or the spacer etch can be performed after the back side nitride etch described later. The front of the wafer of FIG. 1 is protected, for example with a mask (not shown), and the material on the back of the wafer is removed, for example with a wet or, preferably, a dry etch to reduce the stress on the wafer caused by the properties of the nitride. Wafer processing continues, for example to form a first layer of borophosphosilicate glass (BPSG) 32, a layer of tetraethyl orthosilicate (TEOS) 34, and a second layer of BPSG 36 as shown in FIG. 2. A resist layer 38 is patterned over the wafer, leaving exposed the areas of the wafer to which contacts are to be formed.
An etch is performed on the FIG. 2 structure in an attempt to result in the structure of FIG. 3A in which a contact 40 is made to the substrate 10 and a contact 42 is made to the layer of tungsten silicide 16. The layers 12-20A show a stack which forms a portion of the transistors shown (word line stacks). In a conventional process, stopping the etch at the substrate and at (or within) the layer of tungsten silicide (or some other layer) is difficult using a single etch, for example because the nitride 20A etches slower than the BPSG 32, 36. Typically, to achieve the tungsten silicide contact 42 a portion of the substrate will be removed as shown in FIG. 3B, which can result in an electrically undesirable cell. If the etch is stopped on the wafer substrate 10, often contact will not be made to the tungsten silicide 16 but the contact will instead stop within the oxide 18 or nitride 20A as shown in FIG. 3C.
One method of solving this problem is to mask and etch the contact to the substrate, then mask and etch the contact to the tungsten silicide. This process, however, adds a mask step which can create problems with alignment and further adds an additional etch step.
Another method of correcting this problem is described in U.S. Pat. No. 5,498,570, assigned to Micron Technology, Inc., which is incorporated herein by reference. One embodiment of this process forms a mask over the structure of FIG. 1 and isotropically etches the front and back of the wafer. Decreasing feature size with future generation devices increases the likelihood of misalignment, and the solution described in '570 may in some instances result in partial removal of the spacer around the word line stack during the isotropic etch. FIGS. 3D and 3E depict such a problem. Photoresist 25 leaves exposed a portion of spacer nitride 24A and nitride 20A. During an isotropic etch of the FIG. 1 structure to remove layers 20B and 24B from the back of the wafer, layers 24A and 20A can also be isotropically etched as shown in FIG. 3D. Photoresist 25 is removed, a spacer etch is performed, and wafer processing continues to result in the structure as shown in FIG. 3E to form BPSG layers 32 and 36 and TEOS layer 34. Contacts 40 and 42 are etched. During this etch the spacer layer which was damaged as shown in FIG. 3D is further removed along the contact to the substrate which exposes silicide layer 16 as shown in FIG. 3E, and possibly exposes poly layer 14. A subsequently formed conductive plug within contact 40 would short to silicide layer 16 and result in a defective device.
A process which forms a contact to the substrate and to another layer which has a decreased likelihood of damage to a spacer layer, for example from lateral etching, would be desirable.